Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory.
The architectural vulnerability factor (AVF) is a previously recognized parameter for characterizing the vulnerability of the memory to soft errors. Specifically, it refers to a probability that a fault in a particular memory will result in an error. The AVF can be used as the basis for making cost/reliability trade-offs or for determining when to employ soft error detection mechanisms, and it has been particularly useful in the realm of functional safety analysis.
To date, AVF has been estimated using fault injection, where individual faults are simulated across specific memory models. This technique requires countless passes to simulate every possible fault over every model of the different memory structures. Thus, fault injection in a large design with many memories (typically 1000s in large GPUs) is impractical since it would generally take years of compute/simulation time. More information on existing techniques for computing the AVF are disclosed in “Computing Architectural Vulnerability Factors for Address-Based Structures,” by Arijit Biswas, Paul Racunas, Razvan Cheveresan, Joel Emer, Shubhendu S. Mukherjee and Ram Rangan (32nd International Symposium on Computer Architecture (ISCA '05), 4-8 Jun. 2005); and “A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor,” by Shubhendu S. Mukherjee, Christopher Weaver, Joel Emer, 1 Steven K. Reinhardt, and Todd Austin, (Proceedings of the 36th Annual International Symposium on Microarchitecture (MICRO), December 2003).
There is a need for addressing these issues and/or other issues associated with the prior art.